1. Technical Field
The present invention relates to semiconductor modeling in general, and in particular to a method for predicting properties resulting from processes used in the preparation of semiconductor materials. Still more particularly, the present invention relates to a method for predicting the contribution of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation.
2. Description of Related Art
With the current technology, pn junctions are typically fabricated within a silicon substrate by using a low-energy ion implantation followed by a high-temperature thermal annealing. The ion implantation introduces dopant impurities into the silicon substrate, and the thermal annealing repairs any ion-bombardment induced substrate damage while electrically activates the implanted dopant impurities. During the thermal annealing, the dopant impurities often exhibit significant transient enhanced diffusion (TED). TED can lead to severe dopant profile broadening, which poses a great hurdle to fabrications of ultra-shallow pn junctions (i.e., less than 20 nm in depth).
As the size of semiconductor devices continues to decrease, ultra-shallow pn junctions are required to avoid short-channel effects. Thus, a deeper understanding of the underlying mechanisms of dopant TED is needed in order to find the optimum processing conditions for the successful fabrication of ultra-shallow pn junctions. With such understanding, it would be desirable to provide a method for minimizing dopant TED while maximizing the electrical activity of injected dopant impurities.